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| HM5116160A Series HM5118160A Series 1048576-word x 16-bit Dynamic Random Access Memory ADE-203-208C (Z) Rev. 3.0 Jul. 2, 1996 Description The Hitachi HM5116160A Series, HM5118160A Series are CMOS dynamic RAMs organized as 1,048,576-word x 16-bit. They employ the most advanced CMOS technology for high performance and low power. The HM5116160A Series, HM5118160A Series offer Fast Page Mode as a high speed access mode. They have package variations of 42-pin plastic SOJ and 50-pin plastic TSOP II. Features * * * Single 5 V (10 %) High speed Access time: 60 ns/70 ns/80 ns (max) Low power dissipation Active mode: 550 mW/495 mW/440 mW (max) (HM5116160A Series) 935 mW/825 mW/715 mW (max) (HM5118160A Series) Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) Fast page mode capability Long refresh period 4096 refresh cycles : 64 ms (HM5116160A Series) : 128 ms (L-version) 1024 refresh cycles : 16 ms (HM5118160A Series) : 128 ms (L-version) 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) 2CAS-byte control Battery backup operation (L-version) * * * * * This specification is fully compatible with the 16-Mbit DRAM specifications from TEXAS INSTRUMENTS. HM5116160A Series, HM5118160A Series Ordering Information Type No. HM5116160AJ-6 HM5116160AJ-7 HM5116160AJ-8 HM5116160ALJ-6 HM5116160ALJ-7 HM5116160ALJ-8 HM5118160AJ-6 HM5118160AJ-7 HM5118160AJ-8 HM5118160ALJ-6 HM5118160ALJ-7 HM5118160ALJ-8 HM5116160ATT-6 HM5116160ATT-7 HM5116160ATT-8 HM5116160ALTT-6 HM5116160ALTT-7 HM5116160ALTT-8 HM5118160ATT-6 HM5118160ATT-7 HM5118160ATT-8 HM5118160ALTT-6 HM5118160ALTT-7 HM5118160ALTT-8 Access time 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 400-mil 50-pin plastic TSOP II (TTP-50/44DC) Package 400-mil 42-pin plastic SOJ (CP-42D) 2 HM5116160A Series, HM5118160A Series Pin Arrangement HM5116160AJ/ALJ Series VCC I/O0 I/O1 I/O2 I/O3 V CC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 (Top view) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 HM5116160ATT/ALTT Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS NC NC WE RAS A11 A10 A0 A1 A2 A3 VCC 15 16 17 18 19 20 21 22 23 24 25 (Top view) 36 35 34 33 32 31 30 29 28 27 26 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS Pin Description Pin name A0 to A11 Function Address input -- Row/Refresh address A0 to A11 -- Column address A0 to A7 Data input/Data output Row address strobe Column address strobe Read/Write enable Output enable Power supply Ground No connection I/O0 to I/O15 RAS UCAS, LCAS WE OE VCC VSS NC 3 HM5116160A Series, HM5118160A Series Pin Arrangement HM5118160AJ/ALJ Series VCC I/O0 I/O1 I/O2 I/O3 V CC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC NC A0 A1 A2 A3 VCC 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 (Top view) VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 V SS HM5118160ATT/ALTT Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 NC NC WE RAS NC NC A0 A1 A2 A3 VCC 15 16 17 18 19 20 21 22 23 24 25 (Top view) 36 35 34 33 32 31 30 29 28 27 26 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS Pin Description Pin name A0 to A9 Function Address input -- Row/Refresh address A0 to A9 -- Column address A0 to A9 Data input/Data output Row address strobe Column address strobe Read/Write enable Output enable Power supply Ground No connection I/O0 to I/O15 RAS UCAS, LCAS WE OE VCC VSS NC 4 HM5116160A Series, HM5118160A Series Block Diagram RAS RAS Control Circuit UCAS LCAS CAS Control Circuit WE WE Control Circuit OE OE Control Circuit 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array I/O0 I/O1 I/O buffer I/O14 I/O15 Row decoder & driver 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array Column decoder & driver 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array Column decoder & driver 256k memory cell array Sense amp. & I/O bus 256k memory cell array I/O2 I/O3 I/O12 I/O13 Row decoder & driver 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array I/O buffer I/O4 I/O buffer I/O5 I/O10 I/O11 Row decoder & driver 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array Column decoder & driver 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array Column decoder & driver 256k memory cell array Sense amp. & I/O bus 256k memory cell array I/O6 I/O7 I/O8 I/O9 Row decoder & driver 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array 256k memory cell array Sense amp. & I/O bus 256k memory cell array I/O buffer Column address buffer Address : A0 to A7 : HM5116160A Address : A0 to A9 : HM5118160A Row address buffer Address : A0 to A11 : HM5116160A Address : A0 to A9 : HM5118160A 5 HM5116160A Series, HM5118160A Series Truth Table RAS H L L L L L L L L L L L L L H to L H to L H to L L LCAS D L H L L H L L H L L H L H H L L L UCAS D H L L H L L H L L H L L H L H L L WE D H H H L* L* L* L* L* L* 2 2 2 2 2 2 OE D L L L D D D H H H L to H L to H L to H D D D D H Output Open Valid Valid Valid Open Open Open Undefined Undefined Undefined Valid Valid Valid Open Open Open Open Open Operation Standby Lower byte Read cycle Upper byte Word Lower byte Early write cycle Upper byte Word Lower byte Delayed write cycle Upper byte Word Lower byte Read-modify-write cycle Upper byte Word Word Word Word Word Read cycle (Output disabled) RAS-only refresh cycle CAS-before-RAS refresh cycle or Self refresh cycle (L-version) H to L H to L H to L D D D D H Notes: 1. H: High (inactive) L: Low (active) D: H or L 2. t WCS 0 ns Early write cycle t WCS < 0 ns Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output HIZ control are done independently by each UCAS, LCAS. ex. if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected. 6 HM5116160A Series, HM5118160A Series Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage Input high voltage Input low voltage Symbol VCC VIH VIL Min 4.5 2.4 -1.0 Typ 5.0 -- -- Max 5.5 6.5 0.8 Unit V V V Notes 1, 2 1 1 Notes: 1. All voltage referred to VSS 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. 7 HM5116160A Series, HM5118160A Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10 %, VSS = 0 V) (HM5116160A Series) HM5116160A -6 Parameter Operating current* * Standby current 1, 2 -7 Max Min 100 2 -- -- -8 Max Min 90 2 -- -- Max Unit Test conditions 80 2 mA mA t RC = min TTL interface RAS, UCAS, LCAS = VIH Dout = High-Z CMOS interface RAS, UCAS, LCAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, UCAS, LCAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH UCAS, LCAS = VIL Dout = enable t RC = min t PC = min CMOS interface Dout = High-Z CBR refresh: tRC = 31.3 s t RAS 0.3 s CMOS interface RAS, UCAS, LCAS 0.2 V Dout = High-Z 0 V Vin 7 V 0 V Vout 7 V Dout = disable High Iout = -7 mA Low Iout = 4.2 mA Symbol Min I CC1 I CC2 -- -- -- 1 -- 1 -- 1 mA Standby current (L-version) I CC2 -- 150 -- 150 -- 150 A RAS-only refresh current*2 Standby current* 1 I CC3 I CC5 -- -- 100 5 -- -- 90 5 -- -- 80 5 mA mA CAS-before-RAS refresh current I CC6 -- -- -- 100 105 500 -- -- -- 90 95 500 -- -- -- 80 85 500 mA mA A Fast page mode current*1, * 3 I CC7 Battery backup current* (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage 4 I CC10 I CC11 -- 300 -- 300 -- 300 A I LI I LO VOH VOL -10 -10 2.4 0 10 10 VCC 0.4 -10 -10 2.4 0 10 10 VCC 0.4 -10 -10 2.4 0 10 10 VCC 0.4 A A V V Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while UCAS and LCAS = VIH. 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V. 8 HM5116160A Series, HM5118160A Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10 %, VSS = 0 V) (HM5118160A Series) HM5118160A -6 Parameter Operating current* * Standby current 1, 2 -7 Max Min 170 2 -- -- -8 Max Min 150 2 -- -- Max Unit Test conditions 130 2 mA mA t RC = min TTL interface RAS, UCAS, LCAS = VIH Dout = High-Z CMOS interface RAS, UCAS, LCAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, UCAS, LCAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH UCAS, LCAS = VIL Dout = enable t RC = min t PC = min CMOS interface Dout = High-Z CBR refresh: tRC = 125 s t RAS 0.3 s CMOS interface RAS, UCAS, LCAS 0.2 V Dout = High-Z 0 V Vin 7 V 0 V Vout 7 V Dout = disable High Iout = -7 mA Low Iout = 4.2 mA Symbol Min I CC1 I CC2 -- -- -- 1 -- 1 -- 1 mA Standby current (L-version) I CC2 -- 150 -- 150 -- 150 A RAS-only refresh current*2 Standby current* 1 I CC3 I CC5 -- -- 170 5 -- -- 150 5 -- -- 130 5 mA mA CAS-before-RAS refresh current I CC6 -- -- -- 170 170 500 -- -- -- 150 150 500 -- -- -- 130 130 500 mA mA A Fast page mode current*1, * 3 I CC7 Battery backup current* (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage 4 I CC10 I CC11 -- 300 -- 300 -- 300 A I LI I LO VOH VOL -10 -10 2.4 0 10 10 VCC 0.4 -10 -10 2.4 0 10 10 VCC 0.4 -10 -10 2.4 0 10 10 VCC 0.4 A A V V Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while UCAS and LCAS = VIH. 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V. 9 HM5116160A Series, HM5118160A Series Capacitance (Ta = 25C, VCC = 5 V 10 %) Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2 Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. UCAS and LCAS = VIH to disable Dout. 10 HM5116160A Series, HM5118160A Series AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10 %, VSS = 0 V) *1, *2, *18, *19, *20 Test Conditions * * * * Input rise and fall time: 5 ns Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.4 V, 2.4 V Output load: 2 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5116160A/HM5118160A -6 Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Symbol Min t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD 110 40 10 60 15 0 10 0 10 20 15 15 60 5 15 0 0 3 Max -- -- -- -7 Min 130 50 10 Max -- -- -- -8 Min 150 60 10 Max -- -- -- Unit Notes ns ns ns 10000 70 10000 18 -- -- -- -- 45 30 -- -- -- -- -- -- 50 0 10 0 15 20 15 18 70 5 18 0 0 3 10000 80 10000 20 -- -- -- -- 52 35 -- -- -- -- -- -- 50 0 10 0 15 20 15 20 80 5 20 0 0 3 10000 ns 10000 ns -- -- -- -- 60 40 -- -- -- -- -- -- 50 ns ns ns ns ns ns ns ns ns ns ns ns ns 23 22 5 6 6 7 21 21 3 4 RAS to column address delay time t RAD t RSH t CSH t CRP t OED t DZO t DZC tT 11 HM5116160A Series, HM5118160A Series Read Cycle HM5116160A/HM5118160A -6 Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Symbol Min t RAC t CAC t AA t OEA t RCS t RCH t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD -- -- -- -- 0 0 5 30 30 0 3 3 -- -- 15 Max 60 15 30 15 -- -- -- -- -- -- -- -- 15 15 -- -7 Min -- -- -- -- 0 0 5 35 35 0 3 3 -- -- 18 Max 70 18 35 18 -- - -- -- -- -- -- -- 15 15 -- -8 Min -- -- -- -- 0 0 5 40 40 0 3 3 -- -- 20 Max 80 20 40 20 -- -- -- -- -- -- -- -- 15 15 -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 13 5 12, 22 12 8, 9 9, 10, 17 9, 11, 17 9, 25 Write Cycle HM5116160A/HM5118160A -6 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol Min t WCS t WCH t WP t RWL t CWL t DS t DH 0 10 10 15 15 0 10 Max -- -- -- -- -- -- -- -7 Min 0 15 10 18 18 0 15 Max -- -- -- -- -- -- -- -8 Min 0 15 10 20 20 0 15 Max -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns 23 15, 23 15, 23 14, 21 21 12 HM5116160A Series, HM5118160A Series Read-Modify-Write Cycle HM5116160A/HM5118160A -6 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol Min t RWC t RWD t CWD t AWD t OEH 155 85 40 55 15 Max -- -- -- -- -- -7 Min 181 98 46 63 18 Max -- -- -- -- -- -8 Min 205 110 50 70 20 Max -- -- -- -- -- Unit Notes ns ns ns ns ns 14 14 14 Refresh Cycle HM5116160A/HM5118160A -6 Parameter Symbol Min 5 10 0 Max -- -- -- CAS setup time (CBR refresh cycle) t CSR CAS hold time (CBR refresh cycle) t CHR RAS precharge to CAS hold time t RPC -7 Min 5 10 0 Max -- -- -- -8 Min 5 10 0 Max -- -- -- Unit Notes ns ns ns 21 22 21 Fast Page Mode Cycle HM5116160A/HM5118160A -6 Parameter Fast page mode cycle time Fast page mode RAS pulse width Access time from CAS precharge Symbol Min t PC t RASP t CPA 40 -- -- 35 Max -- -7 Min 45 Max -- -8 Min 50 Max -- Unit Notes ns 16 9, 17, 22 100000 -- 35 -- -- 40 100000 -- 40 -- -- 45 100000 ns 45 -- ns ns RAS hold time from CAS precharge t CPRH 13 HM5116160A Series, HM5118160A Series Fast Page Mode Read-Modify-Write Cycle HM5116160A/HM5118160A -6 Parameter Fast page mode read-modify-write cycle time Symbol Min t PRWC 85 60 Max -- -- -7 Min 96 68 Max -- -- -8 Min 105 75 Max -- -- Unit Notes ns ns 14, 22 WE delay time from CAS precharge t CPW Refresh (HM5116160A Series) Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 64 128 Unit ms ms Note 4096 cycles 4096 cycles Refresh (HM5118160A Series) Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 16 128 Unit ms ms Note 1024 cycles 1024 cycles 14 HM5116160A Series, HM5118160A Series Self Refresh Mode (L-version) HM5116160AL/HM5118160AL -6 Parameter RAS pulse width (Self refresh) RAS precharge time (Self refresh) CAS hold time (Self refresh) Symbol Min t RASS t RPS t CHS 100 110 -50 Max -- -- -- -7 Min 100 130 -50 Max -- -- -- -8 Min 100 150 -50 Max -- -- -- Unit Notes s ns ns 26 Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-beforeRAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. (VOH = 2.4 V, VOL = 0.4 V) 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in fast page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH tCWL, the I/O pin will remain open circuit (high impedance); if t OEH < tCWL, invalid data will be out at each I/O. 19. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device. UCAS and LCAS cannot be staggered within the same write/read cycles. 20. All the V CC and VSS pins shall be supplied with the same voltages. 21. t ASC, tCAH , t RCS , t WCS , t WCH, t CSR and t RPC are determined by the earlier falling edge of UCAS or LCAS. 22. t CRP , t CHR, t RCH, t CPA and tCPW are determined by the later rising edge of UCAS or LCAS. 23. t CWL, t DH and tDS should be satisfied by both UCAS and LCAS. 15 HM5116160A Series, HM5118160A Series 24. t CP is determined by the time that both UCAS and LCAS are high. 25. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC/V SS line noise, which causes to degrade V IH min/VIL max level. 26. Please do not use tRASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS 100 s, then RAS precharge time should use tRPS instead of tRP. 27. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 28. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 4096 or 1024 cycles (4096 cycles: HM5116160A Series, 1024 cycles: HM5118160A Series) of distributed CBR refresh with 15.6 s interval should be executed within 64 or 16 ms (64 ms: HM5116160A, 16 ms: HM5118160A) immediately after exiting from and before entering into the self refresh mode. 29. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 30. H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) Invalid Dout 16 HM5116160A Series, HM5118160A Series Notes concerning 2CAS control Please do not separate the UCAS/LCAS operation timing intentionally. However skew between UCAS/LCAS are allowed under the following conditions. 1. Each of the UCAS/LCAS should satisfy the timing specifications individually. 2. Different operation mode for upper/lower byte is not allowed; such as following. RAS Delayed write UCAS Early write LCAS WE 3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP tUL) is satisfied, fast page mode can be performed. RAS UCAS LCAS t UL 4. Byte control operation by remaining UCAS or LCAS high is guaranteed. 17 HM5116160A Series, HM5118160A Series Timing Waveforms*30 Read Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP UCAS LCAS t ASR t RAD t ASC t RAL t CAL t CAH t RAH Address Row Column t RRH t RCS t RCH WE t DZC t CDD Din High-Z t DZO t OEA t OED OE t OEZ t CAC t AA t RAC t CLZ Dout t OFF t OH Dout t OHO 18 HM5116160A Series, HM5118160A Series Early Write Cycle t RC t RAS t RP RAS t CSH t RCD tT UCAS LCAS t RSH t CAS t CRP t ASR t RAH t ASC t CAH Address Row Column t WCS t WCH WE t DS t DH Din Din Dout High-Z** * OE : H or L ** t WCS t WCS (min) 19 HM5116160A Series, HM5118160A Series Delayed Write Cycle*18 t RC t RAS t RP RAS t CSH t RCD tT UCAS LCAS t ASR t RAH t ASC t CAH t RSH t CAS t CRP Address Row Column t CWL t RCS t RWL t WP WE t DZC t DS t DH Din High-Z Din t OEH t OED t DZO OE t OEZ t CLZ High-Z Invalid Dout Dout 20 HM5116160A Series, HM5118160A Series Read-Modify-Write Cycle*18 t RWC t RAS t RP RAS tT t RCD t CAS t CRP UCAS LCAS t RAD t ASR t RAH t ASC t CAH Address Row t RCS Column t CWD t AWD t RWD tCWL t RWL t WP WE t DZC t DS Din High-Z Din t DH t DZO t OED t OEA t OEH OE t CAC t AA t RAC t OEZ t OHO High-Z Dout t CLZ Dout 21 HM5116160A Series, HM5118160A Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t CRP UCAS LCAS t RPC t CRP t ASR t RAH Address Row t OFF Dout High-Z 22 * OE, WE : H or L HM5116160A Series, HM5118160A Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RP t RAS t RC t RP RAS tT t RPC t CP UCAS LCAS t CSR t CHR t RPC t CP t CRP t CSR t CHR Address t OFF Dout High-Z * OE, WE : H or L 23 HM5116160A Series, HM5118160A Series Hidden Refresh Cycle t RC t RAS t RP t RC t RAS t RC t RP t RAS t RP RAS tT t RSH t RCD UCAS LCAS t CHR t CRP t RAD tASR t RAH Address Row t ASC t RAL t CAH Column t RCS WE t RRH t DZC High-Z Din t CDD t DZO t OEA OE t CAC t AA t RAC t CLZ Dout Dout t OED t OEZ t OHO t OFF t OH 24 HM5116160A Series, HM5118160A Series Fast Page Mode Read Cycle t RASP t CPRH t RP RAS tT t CSH t RCD UCAS LCAS t RAL t RAD t ASR t RAH Address Row t CAL t ASC t CAH Column 1 t CAL t ASC t CAH Column 2 t CAL t ASC t CAH Column N t CAS t CP t PC t CAS t CP t RSH t CAS t CRP t RCS t RCS WE t DZC t CDD Din t DZO High-Z t OED t DZC t CDD High-Z t DZO t OED t RCH t RCH t RCS t RRH t RCH t DZC t CDD High-Z t DZO t OED OE t RAC t AA t OEA t CAC t CLZ Dout Dout 1 t OH t CPA t AA t OHO t OEA t CPA t AA t OHO t OFF t OEZ Dout 2 t OEA t CAC t CLZ Dout N t OFF t OEZ t OH t OH t OHO t OFF t CAC t OEZ t CLZ 25 HM5116160A Series, HM5118160A Series Fast Page Mode Early Write Cycle t RASP t RP RAS tT t CSH t RCD t CAS UCAS LCAS t PC t CP t CAS t CP t RSH t CAS t CRP t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address Row Column 1 Column 2 Column N t WCS t WCH t WCS t WCH t WCS t WCH WE t DS t DH t DS t DH t DS t DH Din Din 1 Din 2 Din N Dout High-Z** * OE : H or L ** t WCS t WCS (min) 26 HM5116160A Series, HM5118160A Series Fast Page Mode Delayed Write Cycle*18 t RASP t RP RAS tT t CSH t RCD UCAS LCAS t CP t PC t CAS t CAS t CP t RSH t CAS t CRP t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS WE t WP t DZC t DS t DH Din t DZO t OED Din 1 t DZO t OED t WP t DZC t DS t DH Din 2 t DZO t OED t WP t DZC t DS t DH Din N t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ Dout High-Z Invalid Dout Invalid Dout Invalid Dout 27 HM5116160A Series, HM5118160A Series Fast Page Mode Read-Modify-Write Cycle*18 t RASP t RP RAS tT t CP t RCD UCAS LCAS t PRWC t CP t CAS t CAS t RSH t CAS t CRP t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DS t DZC t DH Din t DZO t OED t OEH OE Din 1 t DZO t OED t OEH t WP t DS t DZC t DH Din 2 t DZO t OED t OEH t WP t DS t DZC t DH Din N t RCS t CWL t ASC t CAH Column 2 t CPW t AWD t CWD t CWL t RCS t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL Address t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ High-Z Dout Dout 1 Dout 2 Dout N 28 HM5116160A Series, HM5118160A Series Self Refresh Cycle (L-version)* 26, 27, 28, 29 t RP t RASS t RPS RAS tT t RPC t CP UCAS LCAS t CRP t CSR t CHS t OFF Dout High-Z *Address, OE, WE: H or L 29 HM5116160A Series, HM5118160A Series Package Dimensions HM5116160AJ/ALJ Series HM5118160AJ/ALJ Series (CP-42D) 27.06 27.43 Max 42 22 10.16 0.13 11.18 0.13 Unit: mm 1 0.74 21 3.50 0.26 2.50 0.12 9.40 0.25 1.3 Max 0.43 0.10 1.27 0.10 30 0.63 Min HM5116160A Series, HM5118160A Series HM5116160ATT/ALTT Series HM5118160ATT/ALTT Series (TTP-50/44DC) 20.95 21.35 Max 40 36 Unit: mm 50 26 1 0.27 0.07 11 15 0.80 0.13 M 25 10.16 11.76 0.20 0 - 5 0.68 0.5 0.1 1.20 Max 0.10 1.15 Max 0.145 0.08 Min 0.18 Max +0.075 -0.025 31 HM5116160A Series, HM5118160A Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 32 HM5116160A Series, HM5118160A Series Revision Record Rev. 0.0 0.1 Date Dec. 27, 1993 Jun. 1, 1994 Contents of Modification Initial issue Addition of HM5116160AL Series Addition of Standby (L-version) max: 0.83 mW Pin Arrangement Addition of Description for JEDEC pin number DC Characteristics Addition of I CC2 (L-version) max: 0.15/0.15/0.15 mA Addition of I CC10 (L-version) max: 0.5/0.5/0.5 mA I CC11 max: 200/200/200 A to 300/300/300 A AC Characteristics Deletion of tCPT min: 20/20/20 ns Deletion of note 25 Change of note 2 Timing waveforms Deletion of CAS-before-RAS Refresh Counter Check Cycle Addition of Self Refresh Cycle 1.0 Feb. 2, 1995 Change of Package type name: TTP-44DC to TTP-50/44DC DC Characteristics I CC7 max: 100/90/80 mA to 105/95/85 mA Change of Package Dimensions: TTP-50/44DC 2.0 Aug. 30, 1995 Change format Change format of truth table Recommended DC Operating condition Addition of note 2 DC Characteristics Addition of note 4 AC Characteristics t RRH min: 0/0/0 ns to 5/5/5 ns Change of notes 11, 12 Addition of note 25: tCP is determined by the time that both UCAS and LCAS are high Package dimensions: CP-42D Package overhang: 1.265 mm to 1.3 mm Max M. Mishima K. Hayakawa M. Mishima H. Iijima Drawn by Approved by H. Yoshioka M. Yamamura M. Mishima H. Iijima 33 HM5116160A Series, HM5118160A Series Revision Record (cont) Rev. 3.0 Date Jul. 2, 1996 Contents of Modification Unification of HM5116160A/HM5118160A Series Change format Addition of HM5118160A-6 Series Pin Description Addition of Row/Refresh address and Column address to address input AC Characteristics Deletion of note 3: Only row address is indispensable on addrress A8, A9, A10, A11 Notes concerning 2CAS control Addition of note 4 Timing waveforms Deletion of note: tOEH tCWE Deletion of notes for RAS-only refresh cycle Drawn by Approved by 34 |
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